1. Field of the Invention
The present invention relates to a flash electrically programmable read-only-memory (EPROM) and, in particular, to an increased-density flash EPROM that utilizes a series of planarized, self-aligned, intermediate strips of conductive material to directly contact the drain regions.
2. Description of the Related Art
A flash electrically programmable read-only-memory (EPROM) is a non-volatile memory that, like conventional EPROMs and electrically-erasable, programmable, read-only-memories (EEPROMs), retains data which has been stored in the memory when power is removed. Although flash EPROMs are architecturally similar to conventional EPROMs and EEPROMs in a number of ways, one characteristic which differentiates flash EPROMs from conventional EPROMs and EEPROMs is that the metal bit lines of the array are utilized to directly contact the drain regions.
FIG. 1 shows a plan diagram of a portion of a conventional flash EPROM array. FIG. 2 shows a cross-sectional diagram taken along lines 1A--1A of FIG. 1. As shown in FIGS. 1 and 2, a conventional flash EPROM array includes a series of metal bit lines MBL1-MBLn which are formed so that each metal bit line MBL contacts each of the drain regions in one column of drain regions.
One of the major goals in the design of a flash EPROM array is to increase the density of the array. Historically, the density of flash EPROM arrays has been increased by reducing the dimensions of the individual cells of the array. One dimension which has proved to be particularly difficult to reduce in size, however, is the area required by each of the metal bit line-to-drain contacts.
The principle reason for this difficulty is the excess area which is required to compensate for any masking alignment error which can occur during the fabrication of the metal bit line-to-drain contacts. As shown in FIG. 2, the metal bit line-to-drain contacts are typically formed by forming a contact mask over a layer of insulation material ILD to define a series of metal contact openings, etching the unmasked portions of the layer of insulation material ILD until a portion of each drain region is exposed, depositing a layer of aluminum which forms the metal bit line-to drain contacts, and then masking and etching the layer of aluminum to form each of the individual metal bit lines.
As can be seen in FIG. 2, if the contact mask is misaligned, the subsequent etching of the layer of insulation material ILD can result in a portion of the word line and poly1 floating gate being etched away, thereby destroying the cell. As a result, the drain regions of the array must be formed to be larger than necessary to insure that, if the contact mask is misaligned, a portion of the word line and floating gate will not be etched away during the formation of the metal contact openings.
Another reason that it is difficult to reduce the area required by each of the metal bit line-to-drain contacts is that aluminum is a non-conformal material. Thus, as the area of the metal contact openings are reduced in size, the non-conformal nature of aluminum prevents the aluminum from reliably flowing into the metal contact openings and forming an electrical contact with the drain regions. As stated above, this application is a continuation-in-part of co-pending application Ser. No. 08/168,756. In the co-pending application, a series of self-aligned, intermediate interconnect strips were formed so that each intermediate interconnect strip directly contacts each of the drain regions in one column of drain regions.
As described in the co-pending application, the intermediate interconnect strips were formed by depositing a relatively thin layer of conductive material over the array, forming a mask over the layer of conductive material to define the intermediate interconnect strips, and then etching the unmasked portions of the layer of conductive material.
One disadvantage with utilizing a relatively thin layer of conductive material is that, due to the rather severe topography that underlies the layer of conductive material, cracking or voids can develop which can open circuit the layer of conductive material.
Therefore, there is a need for an increased-density flash EPROM that reduces the formation of cracks or voids in the layer of conductive material.